Is there a "magic" binary operation from which addition and multiplication can be derived? I planned to make a one instruction set computer (abbr. OISC), and this question arose.
I wanted a "magic" binary operation $*: \mathbb{Z} × \mathbb{Z} → \mathbb{Z}$ so addition and multiplication would be equal to appropriate expressions involving only $*$s.
As I'd want $*$ be an algebraic operation, I presumed $x * y = axy + bx + cy + d$ for some $a, b, c, d \in \mathbb{Z}$.
Then judging by the number of coefficients, I presumed the following identities should hold:
$$
((x * y) * k) * l = x + y
\\
(x * m) * (y * n) = xy
$$
for some $k, l, m, n \in \mathbb{Z}$. The right-hand sides can switch themselves for an alternate solution.
Applying method of undetermined coefficients, the number of equations and the number of coefficients are both eight; they match. The system is quartic though; it would be very hard to find a solution.
Yet unfortunately, I have a strong intuition telling that there is no solution. The identity above for $x+y$ would force its left-hand side to eliminate its $xy$ term. I don't think it would be possible. How can I formalize this idea?
 A: OISC or "One Instruction Set Computer" is not Possible, because it means all Programs are just the single OPCODE repeated, which means all Programs are Exactly the Same !
You must have Branching, Conditionals, Loads, Stores, Etc.
Now, if you want One Instruction to be given to the ALU or "Arithmetic & Logic Unit", even that is not Possible because the ALU does the Conditionals and Bit Operations necessary for Branching.
In case you want to Divide the ALU into AU and LU and then claim that the AU has only 1 OPCODE, that might be Possible.
The Single OPCODE is Increment, based on some Control Bit C, which means it increments the given register when the Control Bit is 1 ; toggle the Control Bit to get Decrement.
Use loops (Branching and Conditional Branching and Bit OPCODES) to calculate A+B via Increments only, by Incrementing A & Decrementing B, until B==0, then A will contain A+B.
Now toggle Control Bit C to get A-B.
Multiplication is repeated Addition, which requires More loops.
In case you are OK with 2 OPCODES in the AU, then consider the 2 OPCODES Addition and Logarithm, with Control Bit C which you can be toggle to get Subtraction and Exponential.
A: A solution close to what you proposed. With 3 registers $r, s, t$, the operation $r + st$ is sufficient for addition and multiplication.
$r = x, s = 1, t = y$ results in $x + y$.
$r = 0, s = x, t = y$ results in $xy$.
Obviously there needs to be some instructions to put $0, 1, x, y$ in the correct registers.
EDIT: actually this operation exists. It's called MAC or MAD.
https://en.wikipedia.org/wiki/Multiply%E2%80%93accumulate_operation
Note that although we are talking here about a low-level CPU instruction, there is a high-level operation that does exactly the same thing: accessing an array element. To access tab[n], one computes $base\_address(tab) + n \times size\_of\_elem(tab)$
