Designing a circuit: Hamming Code How would I design and build a circuit that would generate check bits for 4-bit word?
In this instance, the same circuit should also be used to generate check bits for when you read data back in case of no error, single bit error, or double bit error.
Furthermore, how would I design a circuit that is capable of detecting and correcting a single bit error, in order to detect double bit and to recognize if it is the case of a single bit error, double bit error, or no error?
How would I correct single error in syndrome C4, C2, C1?

 A: The Hamming code for 4 bits would look like this:
$$p_1p_2d_1p_4d_2d_3d_4$$
where $p_1=d_1\oplus d_2\oplus d_4$, $p_2=d_1\oplus d_3\oplus d_4$, $p_4=d_2\oplus d_3\oplus d_4$ and $d_1,d_2,d_3,d_4$ are the data bits. I trust you can easily implement this.
If you also want it to detect errors, you have to add another parity bit $p_0$ which is the xor of all the other bits.
Detection/correction is where the fun starts. You get the code candidate
$$p_0p_1p_2d_1p_4d_2d_3d_4$$ and compute the real value of the parity bits from the data bits you have as above to get
$$p_0^\prime p_1^\prime p_2^\prime d_1p_4^\prime d_2d_3d_4$$
now you xor these two registers and get
$$i_0i_1i_20i_4000$$
Your output will consist of 5 bits: $o_e$ will be $1$ if two errors were detected and $0$ otherwise, and $o_1o_2o_3o_4$ will be the data, corrected if one error was found. The correct way to set them is:
$$o_e = (\neg p_0) \wedge (p_1\vee p_2\vee p_4)$$
$$o_1 = d_1 \oplus (p_1\wedge p_2 \wedge \neg p_4)$$
$$o_2 = d_2 \oplus (p_1\wedge \neg p_2 \wedge p_4)$$
$$o_3 = d_3 \oplus (\neg p_1\wedge p_2 \wedge p_4)$$
$$o_4 = d_4 \oplus (p_1\wedge p_2 \wedge p_4)$$
Any single-bit error in the parity bits would imply the error was in the parity bits themselves.
All of this should be pretty easy to implement.
