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The addition of 4 bit, 2's complement binary numbers 1101 and 0100 is $$\begin{array} \\\hphantom{+}1101\\ + 0100\\ \hline \\ 1 \ 0001 \end{array}$$ there occurs a carry out above, but this will be ignored and the answer is 0001. So the carry out one is an overflow or not? I am learning it myself so if there is any mistake in the context please suggest edits thanks.

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  • $\begingroup$ The overflow occurs when the result too large to be represented, so it actually depends on how many bits you use to represent the result. In your case you're saying the inputs are 4 bits numbers, you're not stating anything about the output. Assuming you want to represent the output using 4 bit as well in your case you have an overflow, otherwise no. $\endgroup$ – user8469759 Jun 2 '16 at 9:45
  • $\begingroup$ Thanks, but the question I encountered in the book is exactly same so isn't it enough to say adding four bits means the framework is 4 bit or the computer is 4 bit? $\endgroup$ – Onix Jun 2 '16 at 11:21
  • $\begingroup$ And if it's not then I think no overflow occurred $\endgroup$ – Onix Jun 2 '16 at 11:22
  • $\begingroup$ I'm observing now you have two complement representation. So the msb's represent the sign, in your specific example you're adding numbers with opposite sign, in that case you don't have overflow, "whatever" the output size is. You can prove the validity of some conditions to check the overflow in general (for example if you add numbers with the same sign, but the output sign is opposite in that case you had an overflow). $\endgroup$ – user8469759 Jun 2 '16 at 11:52
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1101 + 0100 = 0001 is an overflow if it is a wrong answer and not an overflow if it is a correct answer.

If these are unsigned binary numbers then 13+4=1 is wrong, so there is an overflow. In fact, with unsigned binary, a carry out is always an overflow.

But you have specified 2s-complement binary. In that case, (-3)+4=1 is right, so there is no overflow.

With 2s-complement binary, an overflow occurs when the arguments are of the same sign (have the same most significant bit), and the sign (most significant bit) of the result is different. With 2s-complement, the value of the carry out is not relevant to the question of overflows.

Here is a thorough description of overflow in the context of the 6502 processor.

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I do not quite get the question. If the question is "Does there occur an overflow", the answer is yes only if the frame size is 4 bits.

If the frame is 4 bits only, you cannot add these numbers without the loss of the most significant bit. Addition starts at the least significant bit (the right one).

0+1 = 1, No carry
0+0 = 0, No carry
1+1 = 0, Carry value 1
0+1 +1 = 0, Carry value 1
0+1 = 1, No carry
Addition ends here

So in binary form you find indeed 1101+0100 = 10001, and there do occur two carries in the computation. Considering a 4-bit frame the most significant bit will be dropped, so the contribution by the last carry will cause the overflow error.

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