A Boolean expression is given: (A B)’ + B C’ +A’ C = F. Construct the logical circuit and draw the timing diagram of the output F.
I am not sure where to start.
Using Logic Friday 1:
To get a timing diagram, one could assume input signals $A$, $B$ and $C$ and derive the depending signals. For a rough modeling, the delay caused by NAND gates could be assumed as unit-delay, i.e. signal changes are delayed by one unit time "T" at every gate. A more realistic simulation would include the fact that typical CMOS gates have different delays depending on the switching direction of their output. For CMOS technology, a "1 -> 0" transition is typically faster than a "0 -> 1" transition.