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A Boolean expression is given: (A B)’ + B C’ +A’ C = F. Construct the logical circuit and draw the timing diagram of the output F.

I am not sure where to start.

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Maybe you could tell us what kinds of gates you are allowed to use for your logical circuit? The answer might depend on that, e.g. if only NAND gates are allowed, the circuit will be different than if only NOR gates are allowed which will be different than if AND, OR, and NOT gates are allowed. – Dilip Sarwate Oct 10 '12 at 18:19

Using Logic Friday 1:

enter image description here

To get a timing diagram, one could assume input signals $A$, $B$ and $C$ and derive the depending signals. For a rough modeling, the delay caused by NAND gates could be assumed as unit-delay, i.e. signal changes are delayed by one unit time "T" at every gate. A more realistic simulation would include the fact that typical CMOS gates have different delays depending on the switching direction of their output. For CMOS technology, a "1 -> 0" transition is typically faster than a "0 -> 1" transition.

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